As technology scaling of semiconductor integrated circuits continues to improve, it is increasingly difficult to manufacture complex integrated circuits with reasonable manufacturing yields. As feature sizes decrease, the likelihood of having defects on a large chip increases. Even more serious is the problem of the unpredictability inherent in the manufacturing process. The production of integrated circuits is a complex manufacturing process involving many steps. Each manufacturing step has many parameters, which must be precisely controlled to ensure the manufactured devices are as close as possible to being uniform in their characteristics. Any deviation from the ideal value in a process parameter may cause a deviation from the ideal characteristic in the manufactured product, which is referred to as process variation.
Process variation is often translated to high variation in the delay along signal paths within the integrated circuit. In other words, the delay between two nodes of a digital integrated circuit for different manufactured parts of the same design can range from Dfast to Dslow, and the difference Dfast−Dslow is expected to increase in the future as feature sizes become smaller (say, towards 10 nm).
Even more serious is the deterioration of the performance in integrated circuits over time. Greater current densities and higher electrical field strengths in future technologies are expected to accelerate the ageing of integrated circuits, degrading its performance in the form of increased signal path delays until the circuit no longer functions according to specification.
Integrated circuits such as Programmable Logic Devices (PLDs), which include Field-Programmable Gate Arrays (FPGAs), are a type of digital integrated circuit where the circuit functions are not completely defined during manufacturing. The exact function of the logic circuits within a PLD is determined by the user by programming the device. The programming file is known as a “configuration bitstream”, and is generated by the execution of a CAD (computer-aided design) tool flow which includes a “place and route” step and a “bitstream generation step”. The execution time of the CAD tool flow for a latest-generation PLD is typically many minutes to several hours, even on a high-end workstation.
International patent application No. PCT/GB2007/003152 commonly owned herewith discloses a method where the mapping between circuit functions and the actually hardware is not fixed during manufacturing, but can be changed after the device has been deployed, during power-up, or even while it is functioning in-situ.
The present invention discloses a method of delay measurement within a PLD, which may also be applied to other digital integrated circuits which are not programmable in the way that a PLD is.